Modern integrated circuits are constructed with up to several million active devices, such as transistors and capacitors, formed in and on a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polycrystalline silicon and metal, which are etched to form conductors for carrying signals. The conductive layers and interlayer dielectrics are deposited on the silicon substrate wafer in succession, with each layer being, for example, on the order of 1 micron in thickness.
A gate structure is an element of a transistor. FIG. 1 illustrates an example of a gate stack 8. A semiconductor substrate 10 supports a gate insulating layer 16, which overlaps doped regions (source/drain regions) in the substrate (12 and 14), and the gate insulating layer supports a gate 18, which is typically polycrystalline silicon. On the gate is a metallic layer 30. The metallic layer may be separated from the gate by one or more other layers, such as nitrides, oxides, or silicides, illustrated collectively as barrier layer 20. The metallic layer may in turn support one or more other layers (collectively 40), such as nitrides, oxides, or silicides. Sidewall oxide 22 may be formed on the sides of the gate to protect the gate oxide at the foot of the gate stack; and insulating spacers 24 may be formed on either side of the gate stack. Furthermore, contacts to the source/drain regions in the substrate, and to the gate structure, may be formed.
Self-aligned contacts (SAC) allow the design of a semiconductor device to have a distance between the gate and the via contact to the substrate, to be at most one-half the minimum gate width; the contact may even be designed to overlay the gate. Typically, SAC uses a nitride layer on the gate stack, together with spacers that include nitride, to prevent a misaligned contact from electrically contacting the gate itself. If the nitride were not present, then the etch used to form the hole which will become the contact would pass through the dielectric layer all the way to the gate. When present, the nitride layer and spacers act as an etch stop, preventing misalignment from forming a hole all the way to the gate, and therefore allowing design of the device to have a much smaller average distance between the contact and the gate.
The nitride layer on the gate stack has at least a thickness of 800 angstroms when used for forming SAC. If used only for other purposes, such as an etch-stop layer or a hard mask, a thickness of less than 800 angstroms is used. Also, the thickness of at least 800 angstroms is the thickness after the dielectric layer has been formed; the nitride layer is usually thicker when originally formed, allowing for a loss of about 500 angstroms during the gate etch (i.e. thickness for the hard mask function), and a loss of about 200 angstroms during nitride spacer formation.
The nitride containing spacers used in SAC have been formed using low pressure CVD (LPCVD). The high temperatures used in this process, however, have the possibility of damaging the device, particularly in split-gate devices, of very small dimensions.
In a first aspect, the present invention is a method of forming a semiconductor structure, comprising forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.
In a second aspect the present invention is a method of forming a semiconductor structure, comprising forming a nitride layer on a stack by CVD at a temperature of at most 700xc2x0 C., and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer.
In a third aspect, the present invention is a method of forming a semiconductor structure, comprising forming a nitride layer on a stack by CVD, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, comprising tungsten, on the gate layer, and (iii) an etch-stop layer, comprising nitride, on the metallic layer. The gate layer comprises a P+ region and an N+ region, the P+ and N+ regions are separated by a region which is on an isolation region of the substrate having a width of at most 0.4 microns, and the forming and etching are carried out at a temperature and for a time that does not result in substantial diffusion between the P+ region and the N+ region.
The phrase xe2x80x9csecondary amino groupxe2x80x9d means a moiety that contains a nitrogen having two substituents, the moiety being attached through the nitrogen.